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Re: perl
If you have VCS, you can simulate your verilog code directly. What Perl can do is just to automate the flow, for example, you can use Perl to generate some input data (stimulus), call VCS in perl system call, and then let perl to check the result. But basicly, Perl is just used to...
Categorize your size into Random Logic Area + MEM Area.
You can get the area report from synthesis tool, usually it's based on um^2. (Based on the library you are targeting).
The chip area will be (RLA/cell utilization + MEM Area) * (1+DFT overhead)
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