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Recent content by Wall-eee

  1. W

    Current capacity of a microstrip, how do you compute?

    anybody have a reliable formula for computing the current capacity of a microstrip line?
  2. W

    Need help on my thesis regarding insertion loss of my PA design

    this is good solution but my thesis requires just a single ended configuration because my thesis includes cost.
  3. W

    Need help on my thesis regarding insertion loss of my PA design

    shown below are the sourcepull for Gain and large signal S11, using an optimum load impadance derived from max. P1dB loadpull another plot below shows the sourcepull optimum impedances for Gain, S11 large signal and Pout, while using the optimum load impedance @ P1dB
  4. W

    Need help on my thesis regarding insertion loss of my PA design

    just a clarification below statement; "find Optimum Load Impedance with a single tone while the input is driven with 50 Ohm standard impedance" if i understand it correctly, you mean just input a 50-ohm 1Tone power source with an ideal Bias Tee at the gate and then at the output use a Load...
  5. W

    Need help on my thesis regarding insertion loss of my PA design

    according to the manufacturer of this LDMOS, they even have around 1.6 - j 1.4 optimum load impedance for P3dB but their bias setting is different from what i have used so it is quite close... my design process actually started from 1-tone to determine my max. output power and efficiency...
  6. W

    Need help on my thesis regarding insertion loss of my PA design

    oops my mistake...i interchanged my optimum impedance for load and source...my source is 1.5-j1.6...my load is 1.5 - j0.2 by the way, these load and source pulls are based from my 2-tone loadpull simulations.... would you recommend using 1-tone load and source pull isntead?
  7. W

    Need help on my thesis regarding insertion loss of my PA design

    i'm sorry if my topic is not clear...the insertion losses above are just for the passive matching networks. the PA is not included in the simulations yet but I just did load pull and source pull which i then used to design my matching networks. my problem is that i'm having to high Insertion...
  8. W

    What's your tbest technique in Stabilizing your Power Amplifier?

    i totally agree with the issues of adding degenerative resistors at the gate... i have a 4-section LC network. do you recommend all HP network at the input and all LP network at the output? right now, my input network from source (50-ohms) to gate (1.5+j1.6) of the PA is HP-LP-LP-LP with a...
  9. W

    What's your tbest technique in Stabilizing your Power Amplifier?

    hello, my thesis is on a 50W broadband class AB single ended PA design in UHF 480-860MHz. when i simulated the geometric stability as well as K and B, the device is unstable. but i proceeded in designing my matching network...another common stability solution is putting small value resistor...
  10. W

    Need help on my thesis regarding insertion loss of my PA design

    i'm currently working on my masters thesis where i have to design and implement a broadband UHF 50W Class AB PA single ended. i was able to determine the optimum load and source impedance using loadpull simulations..my Zopt= 2 - j1.8 i'm now into my matching network designs at the input and...
  11. W

    What's your tbest technique in Stabilizing your Power Amplifier?

    hello, my raw transistor PA model seems to be unstable for all my desired frequency range at my bias point. 2 questions: 1. based on ur experience, would u suggest doing stability analysis after matching networks of before? because the matching networks will certainly present losses to some...

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