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Here it is : **broken link removed**
But please if you found that this program suits you, make sure that it is quite a good program and try to get in contact with other students who are already involved in their programs to build a vision of how good is the university.
What you see .. isn't...
Hello,
Do you want M.Sc. in Embedded Systems Design --> Microelectronics...
If so I know that NILE UNIVERSITY will be offering M.Sc. and M.Eng. in Microelectronics but I don't know how good is the university and the program are...
It will start for the first time in the university.
Regards
Re: PSL file-Modelsim
Hi,
Here is a do file under the name "do.do" ; it includes all the commands including those that force the signals.
So add this file to the folder including the design.
and then use the command :
do do.do
and check your wave window.
Re: System Verilog
No Simulator Supports all the SV features , but what I said is that ModelSim is the one Simulator that supports MOST of SV features.
Re: System Verilog
Hi,
I know that ModelSim supports most of the SV stuff - whether its design or verification- and you can check the TechNotes to know to what extent is the SV supported.
ModelSim PE student Version (Free Version) : SV design and Verification (Parts ; Assertion Based...
Re: PSL file-Modelsim
Here is what i done ......
use these commands:
vcom DFF_CLEAR.vhd -pslfile DFF_CLEAR_TB.psl
vsim dff_clear -assertdebug
view assertions
Then try to force the signals using the ModelSim GUI .... instead of a testBench
and here is the view i got.
Re: PSL file-Modelsim
Here it is , but it is some how BIG.
The Instructions are in a file "doit.sh", so if you have linux or Cygwin on windows just use "doit.sh demo" ... otherwise just open the file and u can find the ModleSim Instructions.
Its one of the ModelSim examples so you can find it...
how to resolve modelsim set back date problem
It happened once for one of my friends, and the only thing that could be done was to re-install WXP and ModelSim.
So don't you have an image or a restoring checkpoint ?
these features are only supported in questasim.
What i figured that you get this message only if the continuous assignments are inside a generate block.
However, when i ran a simulation the results were ok.
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