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Recent content by wakki1187

  1. W

    Any example of pt2tmax.tcl?

    Hi.. Has anyone ever use the command: source pt2tmax.tcl write_delay_paths -max_paths (value) <output filename> ? I read in tmax user guide it is to import delay paths generated from PrimeTime. but when I used it, the file created only contain the version number of pt2tmax script. How can I...
  2. W

    Primetime and TetraMAX

    Hi. I have generated a .sdf file using primetime. I want to use the .sdf file in tetramax to generate test pattern for path delay fault. But tetramax gives an error saying that the sdf file has parsing error (missing field) at a certain line. So I check the .sdf file and the error was at the...
  3. W

    What tool to be used to generate sdf file?

    Ooo.. but why tmax produce error when I insert sdf file for path delay file? Is it not compatible with tmax?
  4. W

    What tool to be used to generate sdf file?

    Hello. :) There is a function for 'Add delay paths' in TetraMAX that require a file for delay path, and I think I have to use .sdf file for it. Am I correct? or maybe there is another file that I should use? Can someone tell me which tool should I use to generate .sdf file to be used for...
  5. W

    correct syntax to write the port_pin_list needed

    PrimeTime port pin list Hye all.. Thank you for your answers.. They helped me a lot.. :) but I now have problems with operating conditions. Does anybody knows what analysis type is suitable to be used for a combinational circuit? Is it single @ bc_wc?
  6. W

    correct syntax to write the port_pin_list needed

    PrimeTime port pin list ljxpjpjljx: I didn't find any PT example showing how to write the pin list like the one that childs showed. That's why I asked here.. childs: Oh.. So that's how it is.. Thank you for responding.. But what does the a in U1/a means? Does it mean the input? If I have 30...
  7. W

    correct syntax to write the port_pin_list needed

    PrimeTime port pin list Could anyone please tell me the correct syntax to write the port_pin_list? What is it actually, anyway? I just could not understand it even though I have read the tutorial. Please help me...
  8. W

    How can I convert Verilog code (gatelvel) to Schematic?

    I think you can use the software Design Vision from Synopsys to convert verilog to schematic.. :)
  9. W

    What step to run Prime Time?

    do we need to generate .sdf file for a combinational circuit to check the path delay?
  10. W

    .sdf file for path delay fault using TetraMAX.

    Hye everyone. :) I am currently working on a project of generating test pattern for path delay fault for a combinational circuit using TetraMAX. But I don't know how to generate the .sdf file needed to 'Add delay paths' before running the ATPG. I've tried searching for the tutorial on...
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