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I have a question about conversion between MII and RMII interfaces.
I can't find detail information about recovering algorithm of mii_crs signal from rmii_crs_dv signal.
Problem was in rtl compiler optimization process. It's need to preserve correspond instance by command set_attribute preserve true [find /designs -instance *delay_cell*]
I tried to instantiate cell in rtl code. Behavioral simulation was succecful, but compiler diccards instantiated cell.
In rtl code was:
DLY delay_cell(sig , sig_dly);
In output hdl file:
assign sig = 1'b0;
Can I set internal wire in my design as clock signal.
Command define_clock has option {pin | port} But I need to use as clock internal wire from combinational logic.
There is no command 'insert_buffer' in supported SDC commands list.
I need to insert buffer in output hdl file.
I try to use path_delay, but it's not works in my case. May be I used it command not correct.
Hello, i am beginner rtl compiler user. I have a question about synthesis with rtl compiler.
For example, i have 2 signals sig1 and sig2. In verilog code:
assign #10 sig2=sig1;
In synthesis I want to insert delay buffer between sig2 and sig1. Library which I want to use is contain delay...
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