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Recent content by VuTang

  1. V

    Page Table in Linux Virtual Memory Management

    Hi guys, I have read about how Linux kernel manages memory itself and figure out that it uses Virtual Address. To transform from Virtual Address to Physical Address it uses PAGE TABLE. But, where is PAGE TABLE stored? I have already found some articles in Internet taking about this problem...
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    [SOLVED] When do we call that 2 clocks are not synchronized?

    Thank you for your help. After reading your answers above, I come to a conclusion: "If clk1, clk2 are not created by a same source, they will be considered as 2 asynchronized clocks." But, something is not really clear: 1. If clk1 and clk2 come from same source, but have diference period, are...
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    [SOLVED] When do we call that 2 clocks are not synchronized?

    Dear all, Please help me answer question below: Assuming that we have two clock signals: clk1 and clk2, when do we call that clk1 and clk2 are not synchronized? Thank you very much.
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    What is Fast Corner and Slow Corner?

    Hi all, When I am reading about timing analysis in FPGA Designing, I find in my document two new definitions: Slow Corner and Fast Corner and two more related definitions: Max delay analysis and Min delay analysis. Can you guy help me to find out what It mean? Thank you very much. VuTang
  5. V

    [SOLVED] Problem with Parameters in Verilog

    Thanks for your answer, ads-see! I follow your code and it works ok.
  6. V

    [SOLVED] Problem with Parameters in Verilog

    I've already assigned 10 for b, but when parameter 'a' is changed I want to update b's value. How can I do it?
  7. V

    [SOLVED] Problem with Parameters in Verilog

    Oh, I'm sorry, this is my mistake when typing. In my module (design with Vivado-Xilinx): parameter a = 9; localparam b = 10; initial if (a == 1) b = 2, else (a == 2) b = 5; and when I synthesis that module, I got a message: "[Synth 8-1727] cannot assign to non-variable b"
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    [SOLVED] Problem with Parameters in Verilog

    Hi all, I'm designing a module in Verilog and need to use some parameters. For example, I have two parameters: 'a' and 'b' and the value of 'b' depend on 'a'. I use the folow code but It had not run yet. localparam a = 9, b = 10; initial if (a = 1) b = 2; else if (a =2) b = 3; Which...
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    How i can reverse order bits in VHDL code?

    Hi Shaiko, May I have a question? if you use "for" loop like in your code and then implement its in FPGA, what will happen? what difference when I use the follow code in stead of yours? ROLLED_A(0) <= A(31); ... ROLLED_A(31) <= A(0);
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