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setup time in ss corner
Guess the host is more concerned with the uncertainty than exact value?
Anyway...I am also curious about this. Also, if some1 can give insight of the mechanism of setup/hold time, it will be great.
@nd floor said something about data/clock to the storage element, I...
Re: Reg: STA
Not so familiar with STA, however if sizing cells to adjust timing, the whole path needs to be considered. A logic effor point of view should help better with this.
Re: updown counter
My idea is:
First, a DFF with its reverse output feeding back into its data input forms a frequency divider by two.
Put two such divider in serial gives you a two bit counter, counting in one direction (the data output of 1st DFF should be connected the the 2nd DFF, and...
how to implemeny cdma
I'd totally agree with the above, as if you want to implement the whole stuff, then RF, mix-signal, digital and even maybe power has to be concerned.
However, if you are looking forward to implement the digital parts (in my understanding, just deal with digital data in...
Hi,
Thank you all for the help. Guess you are right with the multiple sources of learning and thanks for recommending the websites.
BTW, the guy is a principle engr at Qualcomm, so I guess he may be seeing things in a different point of view...I dont know. The interviewers are all nice, but...
Once in an interview, I said I know some concept of asyn FIFO, and was asked to explain. I drew the block diagram and before I started blah blah about how to control under/overflow, the interviewer said, "Stop, how U design the dual-port SRAM? That's the most difficult part.".
I was so...
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