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Recent content by vpopli

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    Verilog encryption method in VCS to hide hierarchy in simulation and to synthesize ?

    Re: verilog encryption method in VCS to hide hierarchy in simulation and to synthesiz The latest standard for encryption is IEEE 1735 V2. Public key for a tool is required for encryption. You may need to contact tool vendor to get the key and find out whether they are supporting the standard...
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    [moved] how to encrypt part of the verilog code by using 1735 supported pragmas ?

    Re: how to encrypt part of the verilog code by using 1735 supported pragmas ? IP author can encrypt part of IP by enclosing that part of code in protect directives. https://ipencrypter.com provides information and tools for IP encryption. <verilog_code_not_to_encrypt> `pragma protect version=2...
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    IEEE p1735 v2 IP encryption support

    I got some information on **broken link removed** after search on internet. I am still looking for EDA tools available that support this standard.
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    IEEE p1735 v2 IP encryption support

    Are there any EDA tools available that support IEEE Std 1735™-2014 standard (a.k.a. p1735 v2) IP encryption? Also, how can I encrypt my IP to make them compliant with IEEE p1735 v2 standard?
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