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Hi Srini,
Typical set_driving_cell syntax is as below
set_driving_cell –lib_cell FD1 –pin Q [all_inputs]
What the above command really means?
The Above Command implies that all the input ports of the design have the input capacitance value equal to the o/p load of the Flop.
Above syntax...
Hi Srini,
I am not sure , if you are still struggling with the issue.
Before looking into the timing slack numbers,
make sure you have the right constraints
1) proper clock definitions in correct units( DC standard unit is ns , RC standard unit of period is ps )
2) Clock exceptions...
Hi,
All the signal Cross overs from one clock domain to another clock domain, are to be well taken care of through RTL, if any specific synchronizer module provided in the library to be used and set a don't touch attribute on those cells while doing synthesis. I guess syntehsis tool like RC...
Re: floorplanning
HI Tan,
It is not correct notoin that the Analog designs only require the correct floorplanning and for the digital designs the eda tools will take care of the floorplannig !!
Right Floorplannig in my view ::
1) Appropriate placement of the macros / memories in the...
max transition violation
Hi ,
I would like to know the causes for the Max transition time violation ???
I heard that two reasons may lead to this violation
1) input delay of the pin is very high ( more than ) the set value in libary
2) do the wire length that...
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