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Recent content by vlsi_006

  1. V

    diff b/w reset & clear and preset & set in a sequent

    hello, what is the difference b/w reset & clear and preset & set in a sequential circuit. And also, why these signals in any circuit are active low?
  2. V

    Control signals in most of the IC's are active low why?

    Most of the control signals such as reset, CE, etc. in most of the IC's are active low why?
  3. V

    diff b/w synthesis and implementation in xilinx ISE

    synthesize translation mapping Hi, What is synthesis process actually doing in Xilinx ISE?I am using xilinx ISE and as per my understanding, synthesis is a process where we do translation, mapping and optimization to get a netlist. But why r we doing again translation and mapping in the...
  4. V

    pre and postsynthesis simulation mismatch please help

    Thanks for the reply. Sir, i am a student doing my final year project, and i am implementing viterbi decoder in ASIC. The data in RAM and other registers is in '0' state when reset. The address to the RAM is been generated from the block called TBU which has the problem of x-state (therefore...
  5. V

    pre and postsynthesis simulation mismatch please help

    Hello everyone, I have some problem in my gate level netlist simulation. My RTL code simulation is working fine but gate level simulation is not working(getting XXX state). But the design successfully passes the formal verification. Please give me some solution.
  6. V

    Which is the best book about CMOS design fundamentals?

    can any body tell which is the best book for coms design fudamentals
  7. V

    Check my serial to parallel code

    hi is this code correct
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