Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have gnerated the netlist and loaded it in modelsim by invocking from xilinx post translate simulation.
I need to use now testbench could u give me how to load the testbench...for the post translate simulation.
How to generate the test bench file for the post synthesis simulation.
Do i need to...
Dear experts,
While doing post synthesis simulation i am having the error such that it is not able to find the library file paths.
I have complied the library files for the virtex2vp_7 and placed in "D:\xilinx\verilog\src\simprims"
I have given this path in the vsim command options in the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
