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Hello,
I have the following at the output of a PTAT and CTAT which are ok. The problem is that the mirrored current has an offset, which is further amplified when i double it at the output.
Regards,
Vlad
Hello,
I have a basic question, but it seems that i cannot find it's answer.
Assuming we would have a dynamic latched comparator such as the one presented in https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=210039 Figure 2(a).
How would you quantify the hysteresis of such a circuit...
Hello,
I am trying to design a comparator. I have made the one in the images bellow.
However I have problems with making it work for difference voltages < 20mV. I would like a precision of at least 1 mV and delay of a couple of ns.
I want also small current, i'm using 50nA, for the biasing and...
Hello Dominik,
I have tried replicating your results, however I obtain a smaller range ~380 mV. I double checked, however the results differ.
Also you have MP8 and MP10 not biased. Why did you do that?
In the image I attached what I get using my topology, but with the test proposed by you...
This is the most decent level of detail. I don't see why you would want to remove the dots or why does the black bother you. It's in the end just a schematic.
Suggestions regarding the actual problem that I have would be most appreciated.
Regards,
Vlad
Hello,
They are in saturation slightly :); Vgs-Vth is just a couple of mV. But increasing the biasing current, not only has an impact on my noise, but as well on the power consumption. Which i want to keep to a minimum.
I have an impression that what i measure is the common mode input range...
I attached images with results, testbench, full circuit.
I am doing deriv( current from one res + current from the other)
plot the 2 gms as you can see in the image. What i also don't understand is why the gm is the same for both gms. i would expect to see one offseted towards the left and the...
Hello,
I have rail to rail input diff pair, but I have a 100mV linear range (plotted the derivative of the currents in function of input voltage);
Could you please help with some advice on how to increase this linear range. What is more peculiar is that it's that small with tail to rail...
Hello,
I have the following circuit testbench which i presume it's wrong since i have problems plotting the gm.
I do in calculator deriv("current IS in the node of the gnd" ; tried also with a resistor, and still no luck). and I sweep the dc voltage of V4.
Could you please help me?
Thank you
Hello,
I am looking for the paper where this folded cascode class AB output circuit is presented.
I want to understand it better.
Thank you,
Vlad
- - - Updated - - -
Or if anything, if possible to help me understand how this output stage functions
Hello,
I have a not so big circuit to simulate. It's digital and it is composed of 40 counters of 14 bit plus some logic. The simulation in spectre is taking 1 year. In ultrasim extended 1 day, but the data is messed up because of the resolution of the simulation. I am really blocked, because I...
Hello,
I open the start simulation window, select the testbench with the appropriate resolution. I select the sdf file. and enter the region.
In the images you can see the setup and the simulation started without the sdf file.
The structure of the system is the following...
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