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Hi All,
I am planning to use AXI4-Stream interface as a standard interface for inter IP communication(between two IPs) with in FPGA. one IP is ADC IP which forwards samples from ADC IC to DAQ IP. second IP is DAQ IP(data acquisition IP) which gathers all samples from ADC IP. Transaction is...
Hi ALL,
I need a clarification regarding frequency divider using counter.
Usually, If a counter with N bits, it will divide the frequency by 2^N.
reg [19:0] counter;
always@(posedge clk) // clock frequency is 100MHZ
begin
if(!reset_n)
counter <= 0;
else...
Hi All,
I am confused with sampling rate and conversion time. What is the difference between them in data acquisition system?
Could anybody please give me hint on this.
Regards,
Viyaaloth
Hi Dpaul,
Thanks for your suggestion. If i am trying to build my own parallel interface, what are all the things that i need to concentrate. I used only available standard interfaces. while creating my own interface, whether it is needed to compliant to any standard protocol available in...
Okay. Let me ask you two more question.
Is it applicable to create my own parallel interface?. If it possible, then this interface needs to be compatible with any ADC IP that I will create(4-bit ADC, 12-bit ADC etc...). How can I ensure that it is compatible to all ADC IPs.?
If i could use...
Dear All,
Could you please suggest some simple parallel interfaces that can be used for data transfer between two inter IP with in FPGA (in terms of hardware design).
Regards,
Viya
Synchronization logic for DAQ
Dear All,
Can anyone tell me what is the role of synchronization in data acquisition IP in terms of hardware design. Whether synchronization is a mandatory for DAQ IP?
Regards,
Viyaaloth
Re: Generic interface for DAQ IP
still it is in initial stage. Any of the IP's architecture is not yet conformed. I am doing a research on that. what is the suggestion on AXI streaming interface ??.. or Can you suggest any simple parallel interface in which data width can be parameterized. So...
Hi All,
Can anyone tell me about the concept of ping-pong buffer. Whether its a circular buffers including minimum of two buffers?
How it is working..? I am planing to include ping pong buffer in my DAQ IP design. its acquires samples from ADC.
Regards,
Viyaaloth
Generic interface for DAQ IP
Dear All,
I am developing a design which includes two IPs. One is ADC specific IP which will acquire a single sample and returns to the second IP that is DAQ IP. So I need a generic interface between these two IPs for inter IP communication within FPGA. I am...
Dear All,
can anyone tell me about the concept of time stamping.. How can I attach time stamping to each samples from ADC which is stored in a data buffer.?
Regards,
Viyaaloth
Hi Andre_teprom,
Yes. It is using master-slave communication and half-duplex. How it is possible for inter-IP communication. Avalon interface from Altera will be a solution.? whether I can use AXI Stream interface.?
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Hi FvM,
Could you please suggest me some standard...
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