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Recent content by vivsim

  1. V

    what's prebias technology ?

    thanks . Victor
  2. V

    how to simulation PWM small signal model in spice ? thanks.

    i simulated the buck DCDC SSM using spice, PWM using Ridly's model, I compared AC simulation results and Transient results, the two simulation doesn't meet well , i don't know what's wrong, can anyone give me some suggestion ? i think if change ESR , the loop's phase margin is changed...
  3. V

    what is the best way to get a vref in HV process?

    thanks Sec. amp have only 3, if care about driver capibility , a buffer may be added
  4. V

    what is the best way to get a vref in HV process?

    Can you give some suggestion ? thanks in advance. the suppy voltage is a big wide.
  5. V

    Please see the bipolar device layout

    bipolar layout i saw a bipolar layout like this , i think it's a npn, the device is much big , but one diffusion area is very small, why layout like this? thanks in advance.
  6. V

    pass the commands from VC++ program to the command window i

    cadence - language I have learned more, thanks .
  7. V

    Helpt RC's delay time and feedback loop speed , thanks

    1.how to calculate a RC's delay time for a signal? this RC act as a LPF 2. for a close loop , someone said the loop's speed, what's meaning ?, it's bandwidth or something ? thanks in advance
  8. V

    How to test my ESD layout ?

    ESD thing i agree DenisMark. BD is difficult to simulate using spice, maybe some special software can help you. the performance of BD devices is affected by process and other parameters, NBD behave more like a circuit.
  9. V

    How to minimize the output noise for a broadband system?

    can anyone tell how to minimize the output nosie for a broadband system ? which factor is the more important? thanks in advance.
  10. V

    What's the feedfack speed of an OPA?

    feedback speed watersky, thanks. if the buffer means a voltage follower ?
  11. V

    What's the feedfack speed of an OPA?

    what's the feedfack speed of a OPA? if its means 1/BW_3db. thanks in advance ?
  12. V

    Wafer layer thickness

    this information can be got from foundry's EDR file, you can also get from command file . good luck.
  13. V

    The peak current vs. layout

    you can reference foundry's edr rule, in that you can see the DC current density and rms current density of metal, in your case you can take the rms current density for reference.
  14. V

    Information about powerclamps in IC design

    Re: Powerclamp powerclamp is used between vdd and vss, it provide a path for esd discharge, for mutliple power chip, there must be a power rail to rail for providing the esd discharge path. normal , powerclamp circuit can be diode or ggnmos and rail to rail(someone call powercut )circuit can...
  15. V

    how to learn verilogA ?

    learn verilog a i have read the manul of verilogA , i don't think i can design a complex circuit very well, who can provide some papers or training material about verilogA ? thanks in advance.
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