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Recent content by vivekvlsi

  1. V

    Xilinx: 7 series FPGA Transreceiver

    Thanks ads-ee for prompt response and explanation. So as per equation 20*Fref we are calculating line rate as per available frequency in vivado (for example) e.g. 156.25 *20 = 3.125G but if i have 40G seres and using 4 lanes , i.e. 10.3125G per lane , as per equation 10.3125/20 = 515.625 MHz...
  2. V

    Xilinx: 7 series FPGA Transreceiver

    Could any one please tell me the crieteria to select Line rate and their corresponding reference frequency and what is DRP frequency.
  3. V

    color space converter design

    Hi I am going to design a code space converter in verilog. Please help me out in this regard. how should i start my projet ? First of all how to provide RGB data as a input & data out in ycbcr format. Please help me to get quick start in this project..... Thanks in Advance.
  4. V

    VLSI front end engineer (digital)

    Dear Sir / Madam As per your requirement, I am sending you my C.V. I did my "Advanced Post Graduate diploma in VLSI design" from "Semiconductor Complex Ltd." Mohali ( Chandigarh) with (Grade 'A') after my B.E. in Electronics & Telecommunication Engineering (with 74%) & I am having 2.2 years...
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