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Recent content by vivekgaddale

  1. V

    Calibre DRC rule deck

    Hi, I want understand the rule deck file,any sources...pdf for example ... VARIABLE VIA2_W_2 0.5 ----> do this means, VIA in layer2 width of 0.5um VARIABLE VIA1_S_6 0.35 VARIABLE M2_W_5 6 any help regards, VivekG.
  2. V

    How to start DRC/LVS Debug?

    hi, I have got the rule deck & DRC environment, how to debug the drc violation? am using calibre DRV, is the layer mapping different for ICC & calibre DRV?
  3. V

    FIX Hold Violations in different Modes/Corners

    Am using PT, there is scenario, to fix hold , if the setup margin gets violated in different modes, do any one know?
  4. V

    FIX Hold Violations in different Modes/Corners

    HI, Hold violation can be fixed by adding a delay buffer at the Flop, provided the setup violation dont occur at that flop. So adding a buffer, should be done considering the setupmargin. So my question is if the setupmargin doesnt match with the hold in different mode/corner for...
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