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Recent content by vivek kumar gupta

  1. V

    what is the no of equivalence fault in AND gate

    what is the no of equivalent fault in AND gate. what is the no of dominance fault in AND gate.
  2. V

    synchronous write 1 port SRAM depends on:

    synchronous write 1-port SRAM depends on: address change cs rising edge of the RAM clock. please tell me the right option
  3. V

    asynchronous 2-port SRAM depends on:

    asynchronous 2-port SRAM depends on: 1.address change 2.cs 3.rising edge of the ram clock please tell me the right option...
  4. V

    read/write cycles are needed(per bit) to test a 4*4 RAM.

    how many read/write cycles are needed(per bit) to test a 4*4 RAM.
  5. V

    transitions needed to test 4*16 RAM stuck at faults

    how many transition needed(per bit) to test 4*16 RAM stuck at faults??
  6. V

    double synchronization

    in which of the following double synchronization is not possible,when two clocks clkA and clkB are used where clkA - source clock clkB- destination clock 1.clk A has greater freq than clk B 2.clk A has less freq than clk B 3.clk A has double freq than clk B 4.both have same freq but they are...
  7. V

    regarding metastability:

    which of the following is true regarding metastability: 1.depends on setup violation 2.depends on hold violation 3.can be seen as increase in clock to q delay 4. none of these. please tell me the ans

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