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Recent content by VitalyM4

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    Routing of special net (analog) Encounter

    Hello! I have EEPROM in my design and charge-pump. Of course they located inside digital floorplan, but there are several nets between them that should be routed as analog and this nets should be wider than ordinary ones. How to route them with Encounter. Should I use sroute or different...
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    Does Encounter RTL Compiler support SystemVerilog ?

    Hi! Does Encounter RTL Compiler support SystemVerilog for synthesis? Is it feasible to use SV in new projects? It supports well with Cadence tools? Will I have posibility to do mixed simulations? Thx
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    Recognizing shift registers

    Hi! Does anybody know how to force PKS to recognize shift_registers during scan-chain insertion? I have no problem with it in DFT Compiler, but with PKS.... Best regards.
  4. V

    What's wrong with divider

    Could you give an example how to do that? You are talking about finding max?
  5. V

    What's wrong with divider

    I think there is a difference, because variable max finds first 1'b1 MSB in byte and defines number of stages needed for divison. max equal to 0 only in cases 8'b0000_0001 or 8'b0000_0000, so I check for division on 8'd0 and 8'd1, when result equal 8'd255, for all other cases normal divison is...
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    What's wrong with divider

    Thx. I fixed like this. For all who might need it! module div ( SCAN_EN_SCLK , /*Scan Enable*/ SCAN_IN_SCLK , /*Scan Input*/ SCAN_OUT_SCLK, /*Scan output */ rb_por_cr , /*Asynchronous reset*/ SCLK , /*Divider Clock*/ divisor ...
  7. V

    What's wrong with divider

    Hi ! I created divider (255/divisor), it works well for all the cases except one when divisor equal to 1, then result is 0 instead of 255. module div ( SCAN_EN_SCLK , /*Scan Enable*/ SCAN_IN_SCLK , /*Scan Input*/ SCAN_OUT_SCLK, /*Scan output */ rb_por_cr ...
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    SCAN CHAIN for 3 clock.

    scan chain clock domain If it is possible with 1 scan-chan it is good, but how does it impact on ATPG coverage? Another one small question. SCAN_EN_* signals forms inside SPI/U_test_controller why command set_dft_signal -view existing_dft -type ScanEnable -port...
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    SCAN CHAIN for 3 clock.

    stuck-at chain test Hi all! I have design which has 3 different clocks. I want 3 scan-chain - 1 per clock domain, so I need to mux clocks. How to instruct DFT to create 3 scan-chain? I should create 3 test protocols and which clock I should describe there, test clock or clock needed for...
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    Can anyone share SystemVerilog TB with classes

    books on systemverilog in bangalore, india Can anyone share SystemVerilog TB with classes or some tutorial how to use classes in SV? Thx in advance.
  11. V

    How to prevent DFT from changing names?

    DFT changes names After synthesis in DC I have flops in register with names FRAME_COUNT_reg[number] , but after insert_dft it changes names on FRAME_COUNT_reg_number_, how to prevent this name changing. Is there possibility to write netlist in FRAME_COUNT_reg[number] format?
  12. V

    no of stages for mealy and moore machine

    and from FSM encoding type, one-hot gray and so on
  13. V

    Man page viewer error:Man pages could not be found for topic

    page viewer Hello ! I'm working under Mandriva 2007.1 with DC compiler, but man pages viewer doesn't show man pages with messages "Man pages could not be found for topic: " . How can I check if tool were installed correctly? Does anybody knows how to solve this problem? Rgds
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    Using autofix in DFT for resolving violations during insert_dft

    Hello. I have several violation during insert_dft. Mostly C6 - trailing edge port captured data affected by new capture and C26- Clock data different from capture clock for stable cell. How to fix them? Is it possible too to fix them with autofix? Rgds
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    Auto scan-generation Cadence script.

    script autoscan I completely agree with you, but there are different situations. Maybe you know how to make gated-clock element scannable in DFT-compiler? Could you post generic script?

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