Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
thanks for your reply yadav,will u plese consider this query " i took one testcase in 65nm, for that block after adding filler cells i noticed that there is improvement in timing ,at this stage i am not done any change except adding filler cells what will be the reason for improvement in timing?"
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.