Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I want to know about how to construct a 43 tap FIR filter in verilog using "Generate" function in verilog, if you could please guide me, I am trying to make "costas loop " for demodulation and extraction of 8bit data word from 10 bit encoded BPSK transmission at 2 MHz, the system will work at...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.