Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by vishak

  1. V

    what is called fractional delay?

    Fractional delay is a delay which is a non-integer multiple of clock. It is particularly used in sampling where you have to adjust the sampling instants by minute delays so that you get more accurate samples. It is also used in FPGAs as (i believe both are almost the same,but these are less...
  2. V

    Making a harmonizer problem on FPGA

    Find square of magnitude by using the eqn m^2 = real_part^2 + imag_part^2 for every bin. - - - Updated - - - Choose the bin with the max value of square of magnitude by using some sorting algorithm. - - - Updated - - - I believe in the FFT core, bin index is output along with magnitude of FFT.
  3. V

    How to interface a 12/5v fan with a at89c51 microcontroler ?

    First of all check how much current is required for the FAN. Then choose a MOSFET as a switch controlled by the microcontroller to give the power supply to the fan. Sometimes the MOSFET might need an external driver, because of higher threshold voltage and if isolation is needed between MOSFET...
  4. V

    [SOLVED] Is it okay to float the negative output of a differential amplifier?

    It can be done as long as you keep the length of the unused output trace to a minimum in order to minimize capacitance and potential noise coupling.
  5. V

    Making a harmonizer problem on FPGA

    Ouput Frequency of FFT is read with respect to the bins or index output of FFT. Suppose the sampling frequency is 256KHz. Since your FFT is 256 point, each index will correspond to 256/256 ie 1 KHz.Zeroth index represents 1 Khz, 1st index corresponds to 2 Khz and so on. One more thing, the index...
  6. V

    Implementing a LUT with VHDL's DDS Compiler

    dec2bin is the command. The output will be in char. when i said init file , i meant the initialization vector for the ROM module. you can search the xilinx website for the syntax for COE file for ROM initialization. When you instantiate ROM in your design, use the COE file containing the binary...
  7. V

    Urgent Help- Verilog design

    For Edge detector you can use a D flip Flop. Just AND the FF o/p and inverted FF i/p. This gives you the rising edge.
  8. V

    about the doubts in dsp48 slices

    If you use the statement, x<=a*b (provided x is of enough length); then ISE tool will automatically infer a multiplier for the operation using a DSP48 slice. But it won't guarantee the best performance or flexibility. Instead, go to the coregen wizard ,under math operations, select multiplier...
  9. V

    Implementing a LUT with VHDL's DDS Compiler

    First point is to understand how much memory you will need for the application.Since your output word is going to be 12 bits long, you require a maximum of 12x2^12(48 Kbits) bits of memory.If you are going to use the symmetric nature of sine wave then it can be brought down to 48/4=12Kbits...
See more

Part and Inventory Search

Back
Top