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Recent content by vir_1602

  1. V

    Write response of axi

    hi Sammeer Thanks ; ur reply is really useful. Thanks and regards virat sharma
  2. V

    19 bit counter in verilog. Is it possible?

    my dear FVm plz see the 1st post of the anhnna . he has written that he hasn't seen such a large counter, so I was telling where such a large counter can be used at what place and a better altenative Thanks and Regards Vir
  3. V

    Write response of axi

    I have gone through the spec and there is only one line written about it that is "Write response must always follow the last write transfer" and I have also gone through many other sites. all the time I have come on to the above conclusion but still it is not clearly written Thanks and regards...
  4. V

    19 bit counter in verilog. Is it possible?

    hi dick yes it is normally avoided but i wrote this in power saving prospective . by this way we can have less no of transition and such huge counter is required when u want to count a long time period in some block like reset chatter. so it is beneficial to count on slow clock plz correct me...
  5. V

    19 bit counter in verilog. Is it possible?

    Yes it is possible bt dividing the clock and count less is better approach to count higher counts..
  6. V

    Write response of axi

    Hi all can anybody Tell me is write response be always on next clock edge of Wlast signal or there can be delay between wlast and Write response. as far as I have read it is like bresponse is always at the next clock edge of Wlast (i.e when Wlast beat is acknowledged by wready). Thanks in...
  7. V

    AXi read transaction

    yes. ads-ee; through ur post I have understood and I was just thanking shibibn. In last thanks all of u for ur help Thanks and Regards Virat Sharma
  8. V

    AXi read transaction

    Thanks sibibn Regds vir
  9. V

    AXi read transaction

    i am also understanding that spec which is available on arm website... and they have explained write transaction very well but read transaction is unclear... up to now i have thought as we can send directly address and slave will start reading and sending data from that location.. plz correct...
  10. V

    AXi read transaction

    hi shibin Thanks for reply ok so if slave supporting unaligned transfer it can directly send the h1003 as address so suppose rdata is 32 to bit so how many lines will contain valid data as there is no read strobes how can I distinguish Thanks in adv. Thanks and Regards Virat sharma
  11. V

    AXI protocol outsatnding transaction

    first write have to be completed . n sun ray ur lasrtpost is not cleared to me Thanks and Regards Vir
  12. V

    AXi read transaction

    Thanks shibin so u r saying there is both scenario. so if slave do not support unaligned address so what should slave do. and in above scenario; will master send address as h1000. Thanks and regards Virat Sharma
  13. V

    AXI WR and RD channels access same address simultaneously

    yes !!!!! u r write
  14. V

    AXi read transaction

    Hi all does anyone know in read transaction do we send aligned address or starting address. suppose I want to read from location 'h0003. Thanks in adv Vir
  15. V

    AXI protocol outsatnding transaction

    excuse me Mr or Ms. I cant share axi4 spec due to arm's norm. and I said "write traction completed in a order; not out of order" I mean for a master it should receive its transaction as in the order it has sent. - - - Updated - - - hi this will depend upon interface; becuz interface adds...
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