Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi All
This is an interesting question that I Came across in an interview process..
I was asked that when the ASIC is taped out and it is in lab to test you figure out that it is not working fine. Now it is not a logical fault but some sort of metastability issue.
Q1. How can you figure...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.