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Recent content by vipinlal

  1. vipinlal

    Which free editor is best for VHDL/Verilog?

    @MarkPh and @niciki thanks for the suggestion. what plugin are you using for vhdl/verilog for VScode. I see a lot of plugins available, wondering which one I should select.
  2. vipinlal

    Which free editor is best for VHDL/Verilog?

    Is there a way to let the notepad++ editor open inside modelsim as a docked window? Right now a new window opens up and I prefer the codes open inside modelsim as the default editor does.
  3. vipinlal

    Which free editor is best for VHDL/Verilog?

    Thanks for the answers. I have installed and will try out notepad++. On first try, it seems much more awesome than the default editor.
  4. vipinlal

    Which free editor is best for VHDL/Verilog?

    I am currently using Modelsim for editing and testing code. But I feel the code editor is very bad. What editor do you use?
  5. vipinlal

    [SOLVED] System Verilog error in modelsim with enum types.

    Re: system verilog error in modelsim with enum types. I used the following line for this: import enum_types::enum_t; Yes. I tried that too. But then I get these types of errors. ** Error: D:/test.sv(46): (vlog-2730) Undefined variable: 'c'. I have some statements inside the code, where I...
  6. vipinlal

    [SOLVED] System Verilog error in modelsim with enum types.

    I have a design which looks like this: typedef enum { a,b,c d, e} enum_t; module test ( output enum_t test_op, input xx, input clk ); I have a testbench code too where I instantiate module test. module tb_test(); logic clk,xx; enum_t test_op; My question is how do I make the...
  7. vipinlal

    Shift register will parallel load

    I have posted here a code for PISO(parallel in serial out) few years back. Its in VHDL though, but in both behavioral and structural methods.
  8. vipinlal

    VHDL Time Delay Problem?

    If you want to have delay in vhdl without "wait" statement, see this post. https://vhdlguru.blogspot.in/2011/07/delay-in-vhdl-without-using-wait-for.html Another way to implement wait statement for is, by implementing a RAM based shift register. The length of RAM should be equal to (REQUIRED...
  9. vipinlal

    If I have 12 bits each 4 represent a number in binary, how do i convert it to binary?

    you are looking for a BCD to binary converter. Try this code: https://vhdlguru.blogspot.in/2015/04/vhdl-code-for-bcd-to-binary-conversion.html
  10. vipinlal

    Cascaded floating-point operations...reduction possible?

    The only reduction I see is, y1= 1.5f*y0 - x*y0*y0*y0 = y0* (1.5f - x*y0*y0) Just reduces one extra multiplication. Still its too much for a single clock cycle.
  11. vipinlal

    Different division algorithms

    I have the code for restoring division algo here: https://vhdlguru.blogspot.in/2010/03/vhdl-function-for-division-two-signed.html
  12. vipinlal

    How to add bits of a std logic vector and result should be std logic vector

    run a for loop to add all the bits. But if you want a synthesisable design, a for loop will not work. In that case you have to do one addition per clock cycle. and you get the result after 256 clock cycles.
  13. vipinlal

    Is this the right way of implementing fsm

    See this example: https://vhdlguru.blogspot.in/2010/04/how-to-implement-state-machines-in-vhdl.html
  14. vipinlal

    how can i access signals from differents entities within my code in VHDL?

    Few methods are described here: https://vhdlguru.blogspot.in/search/label/port%20mapping
  15. vipinlal

    One cycle delay vhdl

    suppose you want to delay a signal named temp, then you can do it like this: if(rising_edge(clk)) then temp_delay <= temp; end if;
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