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Recent content by vinod.ailsinghani

  1. V

    Verilog HDL - Book Recommendations

    since i am vhdl user,i found it difficult to do code in loose language (free from rules compared to vhdl which on the contrary is completely typed language)often ended up syntax error and unable to write universal code which is both simulation and sythesis compliant.. so firstly, i would like to...
  2. V

    Need help to simulate verilog code in modelsim 6.2c

    Hi friends, I have just enrolled to this community. i am using two EDA tools like Modelsim SE 6.2c and Xilinx 13.2 for verilog RTL coding. I m getting weird problem in modelsim SE PLUS 6.2c while simulating verilog (i.e. adding signal to wave) code like '# (vish-4014) No objects found matching'...
  3. V

    error message "(vish-4014) No objects found matching '/TB_Latches/*'" verilog

    Hi friends, I have just enrolled to this community. i am using two EDA tools like Modelsim SE 6.2c and Xilinx 13.2 for verilog RTL coding. I m getting weird problem in modelsim SE PLUS 6.2c while simulating verilog (i.e. adding signal to wave) code like '# (vish-4014) No objects found...
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