Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Firstly, thank you for your answer...Yes I know it. But gain of this opamps is sufficiently (approx. 75 dB). When I give ideal VCVS (gain = 1) to output, it is ok. Maybe output current make this worst, but its small enought.....
Hello,
I have problem with Opamp transient simulation. I´ve designed several one stage structures (folded, telescopic, symetrical CMOS) and all made same problem. In attachment file is simulation connection - R ratio is 1. So If I have input sinus amplitude 1 V, output amplitude is not 1 V but...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
