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Recent content by vikram161

  1. V

    what is difference between sample and preload boundary scan stage?

    Hello ,,,, Sample is nothing but it is capturing or sampling the values on the I/O's. if there are two chiops on a board lets say A and B . Now A chip's has 2 I/O's lets say . and B chip has 2 I/O's lets say. Now the values of the I/O's on the A chip are captured in to the B chip this is...
  2. V

    EDT TestKompress K19 violation

    K19 simulates the EDT decompressor netlist and performs diagnostic checks if there is a simulation mismatch the help for this is available at the end of the EDT process guide i.e in the appedix section. actually you have to trace back from the scan input of the chain and backwards to the test...
  3. V

    What's the relation between input and output frequency in this image?

    Re: Digital Qusetion what ur expecting can u clarify . r u expecting to find the difference in freq?
  4. V

    i want a tutorial for synopsys DC

    synthesis abc tutorial this is the tutorial for dc
  5. V

    question about initial statement

    this is the book for the synthesis and simulation construct in verilog
  6. V

    Looking for synthesizable VHDL /Verilog code for a simple adpll

    adpll vhdl this is the code u can use DPLL -- MOORE MACHINE //================================================================================= // Title : DPLL // File Name : dpll.v // Project : USB 1.1 // Description...
  7. V

    What is the setup and hold time?

    hold and setup time please go through this so that u will be clear
  8. V

    how can i divide the clock by 3

    i hope this may be useful.. see this link

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