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Recent content by vikasvij1982

  1. V

    STIL file + Tetramax + Modelsim

    Hi, I have generated the top level verilog and also the scan patterns using Tetramax. But since the verilog_single_file command to write patterns has been depricated, I could only get STIL format. My question is that is there a way in which i can directly import the output patterns generated by...
  2. V

    Variable number of inputs in a Verilog module

    Thanks permute for the quick reply, but what i meant with the question was that if i have a new pin name instead of a bus kind of representation for the inputs. That is why i was stating in1, in2 and in3. If i am not clear then please let me know Vikas
  3. V

    Variable number of inputs in a Verilog module

    Hi, I wanted to code a generalized module for a project in which based on the parameters the number of inputs can vary. I know how to have different bit widths based on parameters, but not number of inputs. As an example, if i want to have a module M1 which can have only in1 as input or it...
  4. V

    Preventing Design Compiler optimization to stop at the first violation

    Hi, I have a design which deals with 100's of paths on which i set min/max delays and i would like to know if Design Compiler has any command which actually only gives me the violators out of all these paths. e.g. Suppose say i have path 1, and 2. I individually synthesize path1 and it works...
  5. V

    Synopsys and Cadence Technology files

    technology file tf synopsys lef Hi Shavakmm, Actually i am not talking about .lef files. I am talking about .tf files. I have already converted .lef file using read_lef command, but am not able to link it wil a physical library. Vikas
  6. V

    Help regarding sdf back annotation

    Thanks for you reply. I was able to solve the problem in NC Verilog as i didnt know that i had to use ncsdfc command to convert the sdf file and then make a command file to import the new sdf file into the design. Vikas
  7. V

    Synopsys and Cadence Technology files

    technology file cadence format Hi everyone, I am trying to convert the tool flow from mixed Cadence and Synopsys tools to only Synopsys tools and have a question related to the technology files for the process technology. Is the technology file format for Cadence and Synopsys tools the same or...
  8. V

    Future career in asynchronous design

    Re: Async Design Future Hi, Async design is good but its not necessarily fast. It depends on the methodology used for generating the asynchronous circuits, like delay insensitive circuit, huffman circuits, muller circuits or time based asynchronous circuits. Each have their pros and cons...
  9. V

    Looking for tutorial on min and max delays

    Hi everyone, Can anyone suggest me a good basics tutorial on Min and Max delay settings for Design Compiler and how to generate those constraints in a design. Also if there is any material for basics on race and speed paths, then that would be great. Thanks Vikas
  10. V

    Help regarding sdf back annotation

    Hi everybody, I am stuck in a very odd spot in my tool flow. I am working on some asynchronous modules which is working with synthesized synchronous module. i am able to generate the sdf file using Design Compiler, but i am not able to back annotate this sdf for testing in Modelsim. I have...
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