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Recent content by vikas.m0502

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    verilog code to decide release time

    Hi vardan, Thanks for your reply. But your code is too lengthy. I want something precise. What I want to do is : If write_sel is >16ns then whenever it goes high, 16ns after that release the force. Means as soon as write_sel goes high, 16ns after that i have to release. For this I need the...
  2. V

    verilog code to decide release time

    Hi Mohammed, Thanks for your reply, but whatever is in that link i already know. My main problem is how to give condition with respect to signal's width. Hi Dave, It is the same 'release' what we use as keyword. Yes, I need this forcing for simulation purpose. Like I said before, I have no...
  3. V

    verilog code to decide release time

    Hi, I am trying to release a signal at specific time. For that I need to write a small code in verilog. Condition is : if write_select is 0 for greater than 16ns then release Q after 16ns when write_select goes high. Please let me know if need more clarification. Thanks in advance. Vikas
  4. V

    substitution in c-shell script

    I have one file : mem_x mem_x mem_x mem_x ... mem_x mem_x I want to change this to : mem_1 mem_1 mem_2 mem_2 ... mem_n mem_n I am trying it with csh script but it keeps giving some error. Please help. Thanks in advance.
  5. V

    Issue in pattern simulation

    Hi, While doing no-timing simulation I am getting X-0 mismatches. I observed that the 'Clock' of the failing flops has a ‘x’ on the capture pulse, which is giving mismatch just before the next shift pulse. Tracing it back leads to a clock gate, where the input clock is fine but output is going...
  6. V

    LEC conformal problem

    Analyzing non-equivalent compared points: (G) + 228 PO /serdes6g_cfg_o[des_phs_ctrl][o][2] (R) + 201 PO /serdes6g_cfg_o_DES_PHS_CTRL_O_2 Compare points' mapping phase may be incorrect. Analysis of non-equivalent compared points: Phase mapping. (Occurrence: 1) Any Idea about how...
  7. V

    LEC conformal problem

    yes, thats the problem. Thanks a lot. - - - Updated - - - yes, thats the problem. Thanks a lot. - - - Updated - - - Hi sandeep, Do you know how to match the case in renaming rule. I need to map "i[ib_cal_done][i]" to "i_IB_CAL_DONE_I" (and many more of similar pattern). Thanks, Vikas
  8. V

    LEC conformal problem

    There is no scanin and scanout pins. I have already used the scan constraints. How to decide whether we need to compare them or not ? Actually these are in large numbers like: -Out of 166 PI's only 35 are mapped and 131 are Extra. -Out of 358 PO's only 20 are mapped and 338 are Extra. Doesn't...
  9. V

    LEC conformal problem

    I am getting "EXTRA" in PI and PO while doing LEC with Conformal. Do anyone have idea how to resolve this issue ? I have already used "set mapping method -unreach". This helped in reduction of EXTRA and UNreachable of DFF's but no change in EXTRA of PI and PO. Do I have to map these manually ...
  10. V

    Problem in Conformal

    While doing LEC I am getting following message: " Compared points' data are non-equivalent. Analysis of non-equivalent compared points: Non-corresponding support(s) in the Revised. " -Please suggest how to resolve this. Thanks.
  11. V

    Database for synthesis and pattern generation

    Thanks a lot.
  12. V

    Database for synthesis and pattern generation

    I can write rtl code, but i want big design and don't want to give too much time in designing. Thats why I am asking if you have any link from where i can get netlist or verilog modules.
  13. V

    Database for synthesis and pattern generation

    I just have the tool. I am asking for some database, means netlist,library modules etc. From where can I get that ?
  14. V

    Database for synthesis and pattern generation

    Hi, Thanks for ur reply. But the the thing is I know about dft, all I wanted to know site or link to get all these things to get started.
  15. V

    Database for synthesis and pattern generation

    Hi, Can anyone suggest, from where I can get the database for synthesis and pattern generation through rtl compiler ? I need everything, verilog code(or netlist) library modules everything whatever is needed. Thanks in advance. Regards, vik
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