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By default ,CTS treats set/reset pin of a flop as async r excluded pin.so it does not do clock tracing n skew analysis for Reset pin of flops.but u can make it as a sync pin .
I really dont think u hav gone through the SocUG(soc UserGuide manual) which can feed u with more information on how to...
Clock Period is actually 5ns n same clock is applied for launching n capturing.i have seen that there are number of added in data path.How can i control it? n one more doubt that eating my brain always is ,Is it better to do all domains optimization at a time r domain wise optimization?
Guys How can we build seperate clock Tree for flops n memories?do we have to specify any statements in clockTreeSpecification file?
One more doubt is what is macromodels in clocktreespecification file n How it is useful?
guys please can anybody rectify my problem.
in my project ,
after CTS optimization i am able to clear setup violations.but i am getting large hold violations.but for the same hold violation paths i have large positive values in setup.how can i borrow some amount of time from it.how usefulSkew...
There is no specific amount of space that u hav to keep in between the macros.the spaces in between the macros basically called as channels.if u have more number pins for your macro then u must n should hav to keep the space between them such that u can hav routing with no congestion n the...
guys can any body tell me how i can get the properties height & width of macro in the design so that i can use it in TCL program.I just want to get it through a command in encounter console whenever i select it ,so that i can use it in TCL script.
Thank u in advance.
I
Hi.pavitra
our main aim of power planning is to ensure all the cells in design are able to get sufficient power for proper functioning of our design.
we require no other special libraries for it.we have to load the floorplan completed design for doing powerplanning.
Placing I/O pads is done...
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