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Recent content by vijay43

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    Setup/Hold time violation -- Frequency dependancy

    Set up time is enough to determine the max operating frequency... Max operating frequency is where the setup slack is zero for the critical path.... as the hold violation is frequency independent... please someone correct me if i am wrong.....
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    [SOLVED] How to start study of Analog IC Design?

    thanks for the infoo......
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    STA prime time - timing report

    Hello faizalism, I guess the end of the command is causing some of the path not to be considered.... May be you can just try.. > report_constraints -all_violators -min_delay
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    Static Timing Analysis - two good STA presentations

    For the best understanding of the STA concepts please go through the Prime time fundamentals user guide, also the synopsys timing constraints and optimization guide.... These docs can really be of much help.....
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    Static Timing Analysis

    Set up time and hold time are defined in the library and it varies with the size of the flop.... we can give the input slew and it is also dependent on the input capacitance... the output slew is dependent on the output capacitance.. i mean load....
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    Good Digital Design Questions

    Thanks for the doc..... it is very nice..... - - - Updated - - - Thanks for the doc..... it is very nice.....
  7. V

    vlsi design (physical design)

    @cherry which one is better in tiit... the hyd center or the banglore center...... i m planning to go for tiit...... tell me about that....
  8. V

    vlsi design (physical design)

    @ cherry.... thanks man... i cannot come for that entrance test coz i have a clash with my graduation date for that.... so i m plannng for tiit .... how is tiit... what is your opinion on it...
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    tutorial for mentor graphics ic station

    Hello all... can some body help me in finding a good tutorial to practice floorplan, place and route on mentor graphics ic station.... I am in urgent need of it... can somebody please help..
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    need your valuable suggestion...

    Hello guys... I am doing MSEE in US..... coudnt find any jobs in the field of vlsi.. and planning to go back to india... what do you guys think about it..... are there any who did this way... my plan is to go back and do a short term course in VLSI Physical layout there which would help me to...
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    vlsi design (physical design)

    hi even i am about to complete a masters in US and planning to go back to india... and I am planning to take a short term course in vlsi... I found institutes in hyd and banglore.... vedaiit hyd tiit hyd rv-vlsi banglore can you plz suggest me gud institutes....
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