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Recent content by vijay.kumarreddy

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    What's the reason of having square shaped vias/contacts?

    Hi, Can any one tell me what is the exact reason for having the square shape vias/contacts. Not the rectangle shape. Vijay
  2. V

    metal density at chip level.

    metal density in a chip This is the main reason for the dummy metal fill: Chemical mechanical polishing (CMP) has been used in recent years to planarize interlayer dielectrics. CMP processes are sensitive to layout patterns and this can cause certain regions on chip to have thicker dielectric...
  3. V

    need your advice about this layout.

    The first and formost thing u need to have more gate contact to the input diff pairThis will redice ur gate resistance.cover ur entire gate with gate contacts. AS usual provide dummis on both sides of the diff pair and current mirrors. If this is design is in 90nm or below its better to have all...
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    What is electromigration ?

    Re: ELECTROMIGRATION its just sipmly gradual wareout of the metal due to constat flow of high DC currents if there is not enough width of metal to carry that current. Electromigration will create the hilllocks(shorts) and voids(opens)
  5. V

    How to save and load Virtuoso Bindkeys settings?

    bindkey shift u can add ur own bind key file into ur .cdsinit file sothat it will automatically load ur own bindkeys whe u start ur icfb
  6. V

    WHAT IS THE NEED IN USING PSUB2

    psub2 layer when u have multiple grounds in ur design,while running the LVS u need to seperate the grounds using the psub2 layer. ie if u have 2 grounds say gnda and gndd u need to cover either the gnda or gndd using the psub2 layer. also this ajust an LVS layer not a mask or derived layer. but...
  7. V

    which has more resistance, contact or via ?

    contact resistance is much more compared to the vias as the contact is mixture of the semiconductor and metal where as the vias is just mixture of teh metals. salicid is a special layer cquoting to reduce the resistance.
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    ASSURA VS CALIBRE VS DIVA

    I think calibre is the golden sign off tule in the foundary.
  9. V

    Waffle v/s Stripped Layout

    waffle layout in ic layout in the waffel structure u cannot guarentee the width the of the edge fingers.this is the main disadvantage of the waffel structure
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    Detailed description of the Deep N well

    Re: Deep N well Deep n-well is for the isolation. Guard rings can protect the horizantal currents but can not protect the vertical currents(which can travel deep in to the substrate and can couplr to the nearby sensitive circuits). So deep N-well can prevent vertical currents generated by the...
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    What's the significance of RPO Layer?

    smic sab resistor Its called Resist protection oxide(RPO) used for non salicided area definition.
  12. V

    Calibre RCX warnings: HCELL p18_ckt_rf not located or not allowed

    rcx/calibre.rcx Try giving thr correct path for the xcell file.
  13. V

    What is the Length Of Diffusion effect?

    lod sti You can call this effect also STI (shallo trench isolation effect). Due to this the current in the NMOS and PMOS transistors got effected. To avoide this effect in layout you have to avoide shearing the active regions for the matched pairs like current mirrors ,diff pairs... in...
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    How to block dummy metal fill

    In TSMC you can find DMEXCL(d1 to d8,for all metal 8 layers) layor for the dymmy metal fill exclude.

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