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Hi All,
Which clock we use for capture pulse in SAF patterns? Fast test clk or functional clock?
Also, I can see only one capture pulse for SAF, though we use LOC method in design.
Please can anyone explain?
Hi All,
I am trying to analyse a waveform using simvision loading a shm-trn database. I have dumped the shm file between some patterns.
Would there be any signal dumped which can give the pattern number with respect to the time?
What are Iddq, HVST and Retention tests? What would be the differences in the ATPG setup for creating the corresponding patterns from normal Scan ATPG ?
I see three shift pulse when SE in enabled. So Shift in data of Q 000 means that three 1'b0 are shifted in the scan chain at shift clk right?
Correct me if I am wrong.
Hi I am trying to debug a simulation mismatch. I am viewing the design through DFT Visualizer. I gave the pattern index of the simulated pattern. The visualizer shows 9 bits of data for each pin in the instance. It is something like this.
D 000-000-000 Q 000-100-000-[0]
What does it mean?
Hi, I am trying to debug a mismatch occurred during parallel pattern simulation in BCS. Mismatch is encountered during shift phase. For parallel pattern simulation, the values are forced in D pin of FF's by the simulator. So which pin should I trace back now? D or SI
Kindly correct me if I am...
In a scan chain, is only one MUX is added to make it scannable or for every flop one MUX is added? How do the MUX is added to the sequential logic to make it scannable?
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