Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
thank you very much for replying.I am posting my code which I took from somewhere and modified it....
module add(
input wire signl, sign2,
input wire [3] expl, exp2,
input wire [7] fracl, frac2,
output reg sign_out ,
output reg [3] exp_out ,
output reg [8] frac_out
) ;
// signal declaration...
hello all,
I have two questions-
1.) I have written a behavioral code in verilog that uses some internal registers. During synthesis warning is generated that the signal is assigned but never used in the program so it will be trimmed during optimization part.Will it produce an...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.