Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by VicL

  1. VicL

    Need shematic for ACTEL ISP cable for ProASIC/ProASICplus

    actel devices programming with xilinx cable Are you use Actel`s part? I have some questions. May be by e-mail?
  2. VicL

    Need shematic for ACTEL ISP cable for ProASIC/ProASICplus

    using actel stapl player I have some Q's about it. I`m Altera`s man basicaly. But I`m found that Actels proASICplus devices great substitude. Sorry for my English :oops: :cry: 8) :P :x :twisted:
  3. VicL

    Need shematic for ACTEL ISP cable for ProASIC/ProASICplus

    actel isp Need shematic for ACTEL ISP cable for ProASIC/ProASICplus
  4. VicL

    how to start with Cold Fire - Motorola MCU?

    See this link **broken link removed**
  5. VicL

    :?: CodeWarrior or Multi2000 for Motorola ColdFire?

    CodeWarrior or Multi2000 for Motorola ColdFire :?:
  6. VicL

    What company has the best reputation in xDSL chipset market?

    xdsl chipset Are Infineon SOCRATES chips (SHDSL) is a right choice?
  7. VicL

    Trouble-Free Switching Between Clock

    Download Again:Trouble-Free Switching Between Clocks Trouble-Free Switching Between Clocks
  8. VicL

    Need VCXO PLL Design for T1/E1 (ref. des, methods, etc.)

    Thanks! I have this documents. But VCXO PLL more cheap and effective, IMHO
  9. VicL

    Who can tell me what difference of them? (VHDL)

    May be you have conflict with other design part when dr signal not used in examples 2 and 4?
  10. VicL

    Trouble-Free Switching Between Clock

    Trouble-Free Switching Between Clocks Trouble-Free Switching Between Clocks XILINX XCELL24 Q1`97 xl24_20.pdf & vhdl source
  11. VicL

    Need VCXO PLL Design for T1/E1 (ref. des, methods, etc.)

    We are use MT9076 + MT9042 (PLL) MT9076 have a 2.048/1.544 extracted frequency, and we use MT9042 for 16.384 and some framing pulses generation. But custom PLL more coct effective.
  12. VicL

    Need VCXO PLL Design for T1/E1 (ref. des, methods, etc.)

    RE I have incomming data link E1. I`m need to extract clock and form some framing signal from data stream
  13. VicL

    Need VCXO PLL Design for T1/E1 (ref. des, methods, etc.)

    mt9076 software drivers Need VCXO PLL Design for T1/E1 (ref. des, methods, etc.)
  14. VicL

    Usage of FPGA in hobby circuits???

    pq208 package pcb layout rules I have new UP1 Development Board for sell
  15. VicL

    M@crago® Systems RAVEN - schematics needed

    M@crago® Systems RAVEN Hello! I need schematic of M@crago® Systems RAVEN If anybody have them please PM to me

Part and Inventory Search

Back
Top