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Recent content by vibren.chao

  1. V

    how much voltage can gate-source of a nmos in 0.18um stand?

    If vgs of a nmos be lower than -1V, will the nmos be destroyed?
  2. V

    phase noise waveform can't be displayed after spectre simu..

    I finished a spectre pss and pnoise simulation the noise wave can be displayed but the phase noise wave cannot be displayed when I choose phase noise and click plot the message in CIW is as followed: error, evaluating expression (phasenoise (("pss-fd" ? result "pnoise"))) error, ("difference"...
  3. V

    Capacitor length and width in CDL view

    hi hatebbs, please use CDF to edit the auCdl view of the cap and add parameters of width and length
  4. V

    Problem with exporting CDL with Cadence IC5141

    Re: IC5141 CDL out help hi,sean202 pls use CDF to edit the auCdl view of inv and nand3 and add the params needed
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