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Recent content by vfdff

  1. V

    regarding fatal eroor in xilinx ISE 7.1i during synthesis

    Re: regarding fatal eroor in xilinx ISE 7.1i during synthesi All Platforms 10.1 **broken link removed** **broken link removed** 9.2i **broken link removed** **broken link removed** 9.1i **broken link removed** **broken link removed** **broken link removed** **broken link removed** (MIG...
  2. V

    Generate Loop in Verilog 2001

    verilog for loop assign output reg out; I don't think it is a good style
  3. V

    Fixed Point division in VHDL

    can't be used lmp in stand ??
  4. V

    why is it not synthesizable?

    if (rst'event and rst = '0') then and elsif (clk'event and clk='0') then can't be used in one process !!
  5. V

    How to convert VHDL code to Verilog?

    download x-hdl -crack thanks for your help !! but would you like give me some advise on the use of the program!! for example ,what can I use to open the program,thanks again!!
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