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Recent content by verymiss

  1. V

    Any advice on hierarchical layout to avoid DRC violations on top level?

    add some routing blockages to the sub-modules and some placement blockages(halo) to the boundary of blocks
  2. V

    MacroModel exact definition

    YES,but if this design is a MMMC design.so the syntax is MacroModel pin FEMI/clk 2ps 2ps 2ps 2ps 0fF viewname
  3. V

    Set_multicycle path regarding

    In gerneral,the cycle of setup check is less one than hold check.so the constraint for this path should be set_multicycle_path -hold -1 -from xxx -to yyyy
  4. V

    Importance of SDC in our design

    there is no constraints for design.so there is no time and it has no clks.then optDesign of any stage cannot work without sdc
  5. V

    Importance of SDC in our design

    you can try continue.I make a try tomorrow,and it is true there is no time.
  6. V

    clock network delay difference in primetime with OCV

    This is normal.we know you have set two deraring factors, for lanuch path, the factor is 1, and for capture path is 0.878(1.01/1.15). so when you do report_timing -from flop1/CP, the reg is in the lanuch path,and its delay has no change.then, when you report_timing -to flop1/D ,the reg is in...
  7. V

    [Synthesis] Buffering vs Cloning

    the Cloning is preferred when we want to distribute the load of ICG cells.
  8. V

    What is load balancing in CTS

    some clock trees need insert several clock buffers as load to balance their sub-trees
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