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verylsi

Recent content by verylsi

conversion from verilog to vhdl

I would love to avoid this much big combinatorial logic in the 1st place. but still if you want to write this code in HDL just for simulation purpose then, what problems you are facing ? can you post the whole code, or post the errors if any ?
- verylsi
- Post #2
- Nov 3, 2015
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
look up table in VHDL (not targeting to FPGA )

Can you please elaborate, what exactly you want to design with those look up tables ? BTW, Look up tables are set of all possible values with set of inputs, hope this helps.
- verylsi
- Post #3
- Apr 30, 2015
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
FPGA resource utilization and power consumption

Hi Sumathigokul, Nice question. Please post the answer if you find it from other sources too. BTW, can you please elaborate, which device you are using and what is your operating speed ?
- verylsi
- Post #4
- Apr 13, 2015
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Interfacing FPGA with SPARTAN 6

hi, Its completely up-to you, If you are giving image information through memory stick, you can use the same memory stick to get the image out, you can transfer RGB values and recreate the corrected image through those values, or you can transfer it through USB.. USB is preferred if there are...
- verylsi
- Post #2
- Dec 19, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
instantiation with in an always block

Hi Anusha, When you use generate you should always remember - it is not a run time function. Once synthesis is done for one generated condition , it will not change at run time, as it is hardware inside the FPGA and real electrical connections are made once you synthesize your design.
- verylsi
- Post #2
- Dec 19, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Tools supporting verilog-2001

Hi Anusha, 13.3 supports verilog 2001, also the "part select" ( +: ) was added in Verilog 2000, The Isim should support this.
- verylsi
- Post #2
- Dec 15, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
what is miter? Allegro 16.5 (trace width) how to use this tool

Hi TADE, I believe you should post this on Hardware and PCB section , you will get quicker response there.
- verylsi
- Post #2
- Dec 15, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
regarding time-scale in verilog

Hi, The 'timescale time_unit base / precision base eg. 'timescale 1ps/1ps means thedelays are in 1 ps unit and the precision is 1 ps.. There is no default timescale in Verilog; delays are simply relative numbers, until a timescale directive declares the units and base the numbers represent.
- verylsi
- Post #3
- Dec 12, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Source code -MESA - Horner Bezier

Hi, Can you please post you attempt
- verylsi
- Post #2
- Dec 12, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Concept of Negative setup time

hi, The set up time equation is - Tc2q + Tcomb + Tsetup ≤ Tclk + Tskew Tsetup ≤ (Tclk + Tskew) - ( Tc2q + Tcomb ) Under the condition when Tc2q + Tcomb > than Tclk + Tskew then Tsetup will be negative. So mainly your aim is to design such that that the combination logic is minimal...
- verylsi
- Post #2
- Dec 12, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Offset meaning in programming language

hi, It depends on what context you are referring to. One example.. suppose you have two signals and they have fixed delay and you know the arrival time of 1st signal, then the delay can be considered as an offset and can be added to the arrival time of 1st signal to get the arrival time of...
- verylsi
- Post #2
- Dec 10, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Verilog code for counting pulses in 555timer

Hi, So where exactly you are facing your problem ?.. also you need to re arrange your if else conditions. I mean, error, or understanding wise , A good formatted question will avoid such delay.
- verylsi
- Post #4
- Dec 10, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Spartan 6 TQG144 package DDR/DDR2 interfacing

Hi Ghost, If you can design a memory controller then there is no constraint.. but it is not recommended if there are some time constraints associated. :)
- verylsi
- Post #3
- Dec 9, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
How to create a sine wave using lut in verilog?

Hi Keerthna, I didnt understand your requirement. Are you looking to create Sine Wave in FPGA using some HDL or you want to create a sine wave with LUT approach in a spread sheet ? If you are looking to design using HDL then you can design a ROM and store values ( no. of values are the...
- verylsi
- Post #2
- Dec 9, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Verilog code for counting pulses in 555timer

Yes , definitely, But please post your efforts first.
- verylsi
- Post #2
- Dec 9, 2014
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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verylsi

Welcome to EDAboard.com

Recent content by verylsi

conversion from verilog to vhdl

look up table in VHDL (not targeting to FPGA )

FPGA resource utilization and power consumption

Interfacing FPGA with SPARTAN 6

instantiation with in an always block

Tools supporting verilog-2001

what is miter? Allegro 16.5 (trace width) how to use this tool

regarding time-scale in verilog

Source code -MESA - Horner Bezier

Concept of Negative setup time

Offset meaning in programming language

Verilog code for counting pulses in 555timer

Spartan 6 TQG144 package DDR/DDR2 interfacing

How to create a sine wave using lut in verilog?

Verilog code for counting pulses in 555timer

Part and Inventory Search

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