Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by venu_allipuram

  1. V

    GLIBC_2.0 error with IC5141

    glibc_2.0 cadence All you need to clear this is ... add /lib/i686 to your LD_LIBRARY_PATH variable and see if it works. I believe you should have /lib/i686 on redhat/fedora based linux. Regards VA
  2. V

    How can I measure SNR from sigma delta ADC and decimation?

    sigma-delta snr I guess we can measure by using the fft or Pxx performed on the digital output stream of the modulator.
  3. V

    Bulk Biasing , 0.18um Technology

    0.18um nmos The process is 1p6M TSMC 0.18U Mixed Mode process. Since I have used this process from MOSIS with a design kit, there are 2 transistors which has both bulk-source connected. So this has options of both n-well and p-well with p-well being in the deepNwell as indicated by the above...

Part and Inventory Search

Back
Top