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Recent content by velu.plg

  1. V

    NIOS II Address Width Issue

    I have a QSYS design which has NIOS II, DDR4 emif_s10 IP. DDR4 Configured as data width=72bit, DQ pins/DQS group=4, RAS width=13b, CAS width=10b, AVMM Slave interface's address width (amm_address) =24bit. I need to change the EMIF IP's RAS width from 13bit to 17bit, if I update is change in QSYS...
  2. V

    I2C Clock not generated by master....

    5K pull up is connected as per the spec. Actually am trying to upgrade the Master from cortexr5 to cortexr8. With the cortextr5 FW code i can able to see the the expected behavior. But with the R8 FW code i face this problem and am using the same configuration for both case.
  3. V

    I2C Clock not generated by master....

    Am using DW_apb_i2c IP - Standard mode. I can able to see start bit but after start bit both SDA and SCL is held low. What could be the problem.Here, Processor is the master and I2C device is the Slave.
  4. V

    synplify identify instrumentor......

    I am new to the identify tool. Am just try with simple counter. during synthesis tool throw the below error. Tool : synplify premier 2018.3 Error: No IICE named 'emulater' can be found at line 4 of C:/Users/vbalak1x/Downloads/rev_1_identify_1/HighRel.idc. Command was "breakpoints add -iice...
  5. V

    DDR to AXI INTERFACE.......

    I need Xilinx AXI Master IP name with the data width of 64bit. kindly suggest which Xilinx IP can i use.
  6. V

    DDR to AXI INTERFACE.......

    DDR Memory have 640x400 data. I need to read each 640bits from DDR memory when I get star bit and stored in 640mb internal memory. After getting each 640 bits in a internal memory in need to write this data in to the same DDR with different write location. Platform : zync ultrascal+ Part...
  7. V

    Idelayctrl, idelay, odelay....

    What is the purpose of idelayctrl,idelay,odelay in lpddr2.
  8. V

    FPGA Prototyping of ZSP DSP 900

    1. Sure! i post this question here for people who are experienced in the DSP 900 processor because they can able to provide the better ideas for my DSP 900 startup. 2. DSP 900 processor have any dependency with FPGA's ?? Exactly i want this information. If u have experience with DSP 900...
  9. V

    FPGA Prototyping of ZSP DSP 900

    I have plan to use DSP 900 in my design. Am new to DSP 900 processor. I am going to use the virtex7 FPGA (XC7V2000t) processor for my implementation process. So, please give a reference document or suggestion/idea for prototyping DSP 900 in the FPGA device.
  10. V

    LPDDR3 FPGA Prototyping.....

    1. I have MIG IP for LPDDR2 in Vivado 2014.4. But i need LPDDR3 IP to check to IO level requirements. Any optional ways is there to synthesize the LPDDR3 IP? 2. Currently we have use the windbond LPDDR2 version but i can't find windbond LPDDR3 version in their official website. Please list out...
  11. V

    MIPS interoptive processor FPGA compatibility.....

    not funny! I think you don't have experience in that domain. thanks for your response
  12. V

    MIPS interoptive processor FPGA compatibility.....

    Sure,but we can't achieve same clock frequency as such in ASIC. If you already tried this above scenario means tell me the maximum achievable clock frequency.
  13. V

    MIPS interoptive processor FPGA compatibility.....

    FPGA info: virtex7 , xc7v200t . Is virtex7 FPGA Supports MIPS processor Soft IP. If it's supports the corresponding FPGA means what us the maximum achachievable frequency.And which MIPS series optimized for FPGA?
  14. V

    For I2S interface, add on card type audio codec compatibility......

    i have using Virtex 7 FPGA [xc7v2000t]. For audio processing i need i2s interface and codec. If any add on card type codecs available for Virtex 7 FPGA [xc7v2000t]?
  15. V

    Cortex A5 processor compatibility with FPGA.........

    Yes because i need that clarification itself? With the help of R4 processor we can't achieve 240MHz frequency. For 120Mhz itself we got -1.452ns negative slack[using cortex R4 processor]. If we upgrade our processor[Cortex A7] means shall we rectify this timing issues? If anyone have...
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