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Recent content by velkumargn

  1. V

    Memory cells basic documents

    use the values same .
  2. V

    scripting language for Layout Engineer PERL Or Python

    Hi, For VLSI back end work perl is best one compared with python. Python is playing big role on IoT and some other software domains. no question perl or python is best , they both have benefits based on usage. perl is used by the most of the VLSI company since it is user friendly. good...
  3. V

    Memory cells basic documents

    1) there is lot of freeware available in Google itself. a) for simulation LTspice, ngspice, ORDAD student version,.....like this n number of tools available. You ask which technology it support ? this tools will support for all...
  4. V

    Memory cells basic documents

    Hi, before going with full architecture level of SRAM, first do BITCELL analysis, and SENSE Amp analysis. they both will help you to understand how memory works , then you can move to timing,power area for SRAM . IN BIT CELL analysis you need to do 1) SNM ( Static noise margin -read...
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    Memory cells basic documents

    SRAM 6-T is enough
  6. V

    help for measure current throught MOSFET using ltspice.

    i am doing bitcell analysis of 6T-RAM for measure current through MOSFET I cant use .measure TRAN ION1d i(XI.MNN1) FROM=0n TO=1000n LT Spice not finding current through MOSFET. But I can find node current using .measure tran Ion find i(vdt) at=10n (as a voltage source current). Can...
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    What is the significance of double dummy poly on both sides for every transistor?

    Re: Double dummy poly in deep submicron technologies 193nm lithographic process near UV light grid light will diffracted, so UV will go and form gate at some other place. If drain or source will come that place additional device will form with DRC. to avoid that we add dummy poly . Due to...
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    What is the significance of double dummy poly on both sides for every transistor?

    Re: Double dummy poly in deep submicron technologies poly is formed by Uv light. duo to diffraction at grid of UV light. another gate will form near to actual gate . to avoid that we r placing dummy poly . this will cancel the additional poly by distractive interferes
  9. V

    Internship in VLSI in India.

    If you know RLC networks,Differential amplifiers,Current mirrors. Comparator and Opamp design. you must implement it on virtuoso or SPICE tool...Try for analog simulation Jobs
  10. V

    List of small and middle sized vlsi company in bangalore?

    Thanks for your post, I have Applied Nvidia, Broadcom, Intel, Infenera, Infinion, sicon and some more company who has opening . But no one gave response. I am ready to work for low salary too, if it is vlsi firm. If possibe help me out get job in VLSI Design - - - Updated - - - By linkedIn...
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    M.Tech VLSI Fresher looking for a job in Bangalore

    \[\sin\]\[\sin\]\[\sin\]\[\sin\]\[\sin\] tanks for your post. sattva etech having opening for 3-4 year experience not for fresher
  12. V

    M.Tech VLSI Fresher looking for a job in Bangalore

    hi, I am Velkumar, completed M.E VLSI Design in RMK Engineering College and secured First mark in M.E with aggregate of 8.8 CGPA. I have worked in DRDO as a trainee for SATA IP Core Development using Verilog HDL. I have hands on experience in EDA tools such as Cadence- Virtuoso, RTL Compiler...
  13. V

    List of small and middle sized vlsi company in bangalore?

    Any one can list small and middle sizes VLSI Company in Bangalore. I have Completed M.Tech. VLSI , Did myM.Tech project in CAIR,DRDO Blore, and IIT-M. but i dont l kow how to get job . I am holding 90% mark, experience with Virtuoso , SOC encounter, Design Compiler, Tetra max(DFT)
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    How to fill a RAM using VHDL code?

    I am new for VLSI if you get .Pls forward to me. I am creating FFT processor for that I need SRAM
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