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Recent content by vcnvcc

  1. V

    Fault Grading: About EQ fault

    Hello I wanted to know about EQ fault (Equivalent fault), which we see in Tessent report. I have check Tessent manual. what I wanted to know is - 1. Is fault is equivalent to another fault? if yes, how do I check/know about it? 2. what are steps to look at such fault? 3. would help if you...
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    Always-on power domain voltage

    Well first of all thanks for reply! I looked at your post 3 times consecutively since I opened your post today, kept “smiling in mustache”!! About post: I think I have asked/written incorrectly, but more info I can’t put here...anyway thanks again for reply..
  3. V

    Always-on power domain voltage

    Thanks for reply.. ~Sam :-) Some chips what I saw have alway-on domain placed with higher voltage. (if it has 3v & 5v, then AoN domain is on 5v) that is why this query came up.. - What made you to write this comment.. whats wrong in 3.3v. I am 100% sure that there is some significance in...
  4. V

    Always-on power domain voltage

    Lets assume - I have 2 voltage domain - out of which 1 is always-on. My chip has 1.2V & 3.3V Now my question is - Why always-on power domain's logic will sit on 3.3V? why not 1.2 V Please share your experience, if you want to add please do so.. Thank you.
  5. V

    supply sequencing in Low Power ASICs and On Board

    Before my question this is the assumption - I am assuming Supply sequencing is same - within ASIC which has many power domains, and within ICs which are sitting on Board. 1. What is the need of supply sequencing within ASIC which has multiple power domains. 2. If we don't follow it what are...
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    difference between I2C PAD and GPIO PAD

    In SoC chip, what is difference between I2C PAD and GPIO PAD? I know that - I2C PAD is special pad which is not GPIO. there will be pullup on these PADS. But would like to know the insights. Did my homework, but no success... So asking you, can you please share your insights? Thanks..
  7. V

    ARM AHB/APB question

    Thank you Guys for your reply!! Yes.. That caught my interest, how that paths are cut down? - is that something which even we come across called pipe-lining? to fix timing at RTL? or some other concept which has been implemented to fix timing for such huge combo??
  8. V

    Examples of ICs with very low pad count

    I think what you are looking for is SoC which has less number of I/O.. Am i right?
  9. V

    ARM AHB/APB question

    I have question on AHB Bus – Question – 1 (related to issue faced in closing timing.) Basically I am new to ARM & its Bus protocol, I have just started to work on it, so have lot of questions. I am referring to this diagram e.g . **broken link removed** Can I say that arbiter + muxes +...
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    Have Question on verilog

    Can you help me understanding this my_ByteSel = {8’d3, 8’d3} WIDTH = 8 my_pointer (value) `WIDTH * (value) +: `WIDTH Wire [10:0] my_counter; this is what I would like to understand --> my_counter(my_ByteSel[`my_pointer(i)]) assume that value will take  0 and 1 – only two values...
  11. V

    Verilog assignment query

    Input [3:0]Flow; assign {a_flow, b_flw, c_flow} = { flow[‘a_flow], flow[`b_flow], flow[‘c_flow] }; I donot understand it – can you please help Does it mean assign {a_flow, b_flw, c_flow} = flow[3], flow[2], flow[1] OR assign {a_flow, b_flw, c_flow} = flow[2], flow[1], flow[0] Thanks
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    Question on DFT - scan insertion

    Hello, When we say DFT – it all comes when I use synthesis (it is understood that I have to decide dft architecture, scan compression, scan chain no), and give it to synthesis scripts and dft compiler will insert scan in netlist. But if I take a look at rtl level – Not IP level, what should I...
  13. V

    DC topographical - Cadence Encounter

    Hello.. I am using Cadence Encounter, Now I would like to run DC topo. What file do I have to use to run DC topo. Can you please describe, how do I proceed? Thanks.
  14. V

    what is the max transition and max capacitance

    So rca - Lets consider PT - so all you are saying is first of all check for Max trans/cap, fix it, and then you check setup/hold and fix it?? Am I interpreting it correctly? Now if we go back to DC - Is the same holds true? I know that we'll not fix hold in DC (provided it is not huge) Can you...
  15. V

    How the gate count of a design is determined?

    I am asking this w.r.t. DC synthesis QoR report - QoR report says all area Combo area & non combo area; along with that it also says Black box area. Now my question is while calculating area for Die size estimation - DO I have to consider this black box area as well? I think - I should take...
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