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Recent content by vbharath

  1. V

    ATPG and pattern Simulation mismatch (Sirial and Parallel) ?

    1:- whys do we prefer serial simulation over parallel? what is the difference? why we are generating both serial and parallel patterns?
  2. V

    ATPG and pattern Simulation mismatch (Debug pattern 1/0 and 0/X) ?

    Hi 1.) Can any give source for simulation mismatch, if possible explain with one example? 2.)Why do we do no timing simulation, what would be the reason for doing no timing simulation what errors we may get in no timing simulation and how to debug? 3.)why latches are made transparent during...
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