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Recent content by Vasilevski

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    Tantalum capacitors damage problem

    Sorry, I havent got what we should derate on your opinion. If you meant the voltage that is applied to the tantalum capacitors, I can say that we apply 70% of the rated voltage which is more than enough since the manufacturers recommend only 20% margin. We don't do 100% IQC test on reeled...
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    Tantalum capacitors damage problem

    Hi, Thank you for your reply! I agree with you upon mechanical stress. Nevertheless, analysing our manufacturing process, I can think of the only reason of getting micro cracks and it is too rapid cooling after solder reflow. I have discussed this idea with our Process Engineers and they have...
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    Tantalum capacitors damage problem

    Hi, Thanks a lot for the tech paper from Kyocera. I'll discuss it with our PE's. For now I can say, that the Peak temperature of reflow for lead free process is set to 250C for our assemblies. Possibly, it can lead to a higher failure rate of the caps. Now I'm thinking of gluing 50-100 caps to...
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    Tantalum capacitors damage problem

    Hi, Yes, it's really fortunate. The failure rate due to the tantalum capacitors on a customer side is around 0,0005%. Yes, we tried to figure out is there any coherence between the failures of the capacitors and the components nearby but it seems that there is not. If we replace the capacitors...
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    Tantalum capacitors damage problem

    Hi. Thanks for the answer! It seems like the problem is not related to inrush currents since it appears in different PCBs in different places. Nevertheless, we considered that it can be an issue and conducted the following experiment. We have different types of PCBs where we have faced the...
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    Tantalum capacitors damage problem

    Hello all. Straight to the point. I work for an electronics company. We deal with a manufacture of power supplies 1-4kW. We have a tantalum capacitors malfunction problem from time to time. We usually use AVX or Kemet tantalum capacitors. An annual consumption of the capacitors usually is...
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    IEC 60601-1 Minimum CREEPAGE DISTANCES and AIR CLEARANCES

    Hello all, I have a task to modify a power supply in accordance with IEC 60601-1 (3d edition) and provide 2 MOPP safety. Sometimes it's not easy to me to understand what this standard requires because I've never deal with it before. Here my question: In the section "8.9 * CREEPAGE DISTANCES and...
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    Is this LED current ripple going to be visible as flicker?

    Looks like this is a slippery theme. Did you see this article? You should distinguish requirements for LED flicker and personal perception (every man to his own taste). You can arrange your own quiz and ask all your acquaintances can they see flicker or not. You can find out about requirements...
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    Is this LED current ripple going to be visible as flicker?

    Do you mean power-line flicker or just LED flicker? In both cases I'd say "no" but I assume you want to have proofs. May be these links well be helpful: https://en.wikipedia.org/wiki/Power-line_flicker#Measurement_of_flicker https://amsdottorato.unibo.it/3270/1/Masi_Maria_Gabriella_tesi.pdf...
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    Components size and PCB trace

    Hi, As was mentioned above there are no reasons you can't use 1206 or 0805 in your PCB layout. 100 kHz is quite low frequency and parasitic inductance and capacitance will not cause a significant impact. Our firm is a manufacturer of the power supplies (1-4kW) that's why we use quite big PCBs...
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    Tolerance of capacitor value?

    Hello, Looks like these capacitors are quite rare. I think you are able to order them with request only (by phone or email). There aren't any signs of the Part Number for this type of capacitors on their cite. Google query "capacitor "E type" site:http://www.ftcap.de" didn't help either...
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    Altium 15 - via diameter does not appear in PCB Inspector when using FSO

    Hi, I know one case which can cause such situation. If at least one of the VIAs has the value "Top-Middle-Bottom" in the "Stack mode" you will get what you have. Altium doesn't let you change diameter of VIAs which have the same diameter but different type of Stack mode using the PCB Inspector...
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    Altium stitching via issue

    Hi again, What do you want to get at the end: two Polygons stitched by VIAs or a 'thieving pattern' on signal layer? It's not clear for me still. I didn't face with Mentor graphics and it makes things more complicated. If you want to get stitched Polygons you should have two Polygons which are...
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    Altium stitching via issue

    Hi, I'm not sure I understand clearly what bothering you, but here's my answer: I Altium VIA stitches (clings) to the polygon or trace beneath them automatically. If you place VIA on two different traces (they cross each other in different layers and are conected to different nets) pop-up menu...
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    Transition from Sn/Pb to Lead-free soldering (RoHS), possible unexpected problems

    I'd rather say it's awful:) Sometimes the conspiracy theory looks pretty convincing:) Thank you very much for the interesting article. Unfortunately, it reveals reliability questions only. I still eager to know any information for questins 1,3..5 from my list. And one more question for you. Do...

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