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I used ModelSim years ago, it hadn't such possibility. Check the website for the current status.
In the flows I worked with, Verilog-A will require analog simulator. Standalone Verilog-A design (without Verilog-D) can be simulated by some SPICE simulators.
Hi,
There is a Verilog (in the context it may be referred as Verilog-D) to model digital processes, there is Verilog-A to model analog processes. Verilog-AMS allows modeling both analog and digital processes in the same module. You can consider that Verilog-D and Verilog-A are subsets of...
Yaso,
Synopsys has several analog simulators that support Verilog-A. As far as I know, only HSPICE creates *.tr0 files during transient simulation.
Do you use HSPICE?
Assume that you have a Verilog-A module, that is instantiated in SPICE deck. Substitute it with a dummy SPICE subcircuit. If...
Did you simulate the code or just compiled?
It worked for me. If it is simulator specific issue, add timing delay before $fdisplay. Like "#10 $fdisplay..."
Difficult to understand the purpose of the code.
Prefer to do file I/O in the top module.
I understand that you netlist your design then simulate it with HSPICE (.tr0). To debug look into actual netlist that is simulated. Are there statements like .print. .probe. .plot? .tran?
When input files are correct, Verilog-A is handled properly :)
Regards,
Vardan
You may also encounter "Look Up Table(LUT) implementation of a boolean function". It's almost the same. Assume inputs form address of a ROM, and it's cell programmed to output values from your table.
There are many ways to implement a multiplexer. One with transmission gates can work for analog buses.
Transmission(pass) gate is a basic building block in IC design. Search the web for "multiplexer transmission gate".
always @(negedge write_sel)
t2 = $time;
always @(posedge write_sel)
if (($time-t2) > time_limit)
$display("\n\tTime to release Q");
It's not a case to use $width. See if you can optimize the code.
Think by register you mean reg type variables. The assignment is done exactly in the same way as assigning 1,0,x. Inside initial or always block, do blocking or non-blocking assignment.
You'll need to assign "Z" values in testbenches or when bidirectional buses are modeled.
always ...
...
Task is not clear. >16ns or when write_select goes high?
I would suggest using time variable
See example code below. Adjust time_limit parameter to the timescale.
`timescale 1ns/1ns
module test1();
parameter hi = 1'b1, lo = 1'b0;
parameter time_limit = 16;
reg write_sel;
time t1, t2...
Hi Vinod,
First open file using $fopen task in an initial block.
Then you can use $fdisplay task. Let's assume your number changes on rising edge of the clock, then I would read its value on falling edge
always @(negedge clk)
$fdisplay(fid1,"%d", theNumber);
Before ending simulation you'll...
Assume you need an edge detecting circuit.
assign out = Q1 & (!Q2);
always @(posedge clk or negedge rst)
if (!rst)
begin
Q1 <= 1'b0;
Q2 <= 1'b0;
end
else
begin
Q1 <= In;
Q2 <= Q1;
end
Re: Even binary counter from binary counter...................
This is binary counter output sequence:
0000, 0001, 0010, 0011, 0100,...
0 , 1 , 2 , 3 , 4 ,...
Just add a bit after LSB of the counter above, and tie it to 0.
00000, 00010, 00100, 00110, 01000...
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