Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Vaibhav Singh

  1. V

    Urgent - Liveness of an assertion in Verification , Rulebase

    Hi I need help with this question: if i have an assertion if a is true b is true eventually My question is -- till what time will my Rulebase check this assertion and say if it passed or failed.That is for how many cycles will it check for this assertion to pass if a never became true. Also...
  2. V

    How to decide whether to use moore FSM VS or mealy FSM?

    Hi All I have a question hope you guys can help how do we decide which when to use a moore FSM VS a mealy FSM in which circuit does it have something to do with the fact that moore needs an extra state and an extra clock cycle for the output to show?? Please help?
  3. V

    Where do we use latches and where do we use flip flops?

    Hi All I have a question hope you guys can help I know that a latch is level sensitive and a flip flop is edge sensitive how do we decide which unit to use in which circuit or where do we use latches and where do we use flip flops and why ??
  4. V

    help needed regarding verification

    Hi I am new in the field of Verification Can anyone please upload or provide the link for the book : writing testbench:functional verification of HDL model.by janick bergeron 2nd edition Your help is highly appreciated
See more

Part and Inventory Search

Back
Top