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I need information regarding specification of manufacturing process (standard cell libraries).
I designed a digital core, and i need to estimate how much power will it take and what would be the size.
i know that a rough estimation use NAND2 specification for example uW/MHz and cell size...
Hello,
Although this subject is highly discussed everywhere, i couldn't find a decent answer to the questions regarding estimation of VLSI and logic design. By estimation i mean not using EDA tools that perform power analysis or an existing synthesized deign.
I'm referring to the thumb rules...
Hi amnakhan786,
I'm trying to use AVR (AVtiny preferred) with a fast SPI (~8 MHz). most DS claim to require high voltage power to support higher frequecies, and also the SPI is 1/2 of system freq.
How did you connect >22 MHz f_osc? what voltage you use?
Thanks in advance,
uzi
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