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Hi all,
My ADC chip has very low resistance between its supply pins (VDD and GND) for the digital part (ananlog part is fine its in Mohms range). It is almost 600ohms with VDD of 1.5V. So digital part which should not draw any static current must be consuming about 3mA of current without any...
thanks buddy,
I found the mistake I was making which was very stupid of me then.
When one changes the config view, he must run the testbench using config view (not with the schematic view). Rest worked great. However, I did not use your spectre method which seems a bit complicated to me...
Hi erikl,
In your pdf, you mentioned "Now, within ADE add the netlist to the model setup". I dont understand this point. Can you please elaborate on this point.
Also, do you have experience using calibreview. I got the extracted view from the layout in calibre format. But the calibre view gave...
Hi all,
I did extraction from calibre xRC and got "calibre" view. When i simulate it by changing the config view of the testbench I get the same simulation results as that of schematics.
Where I am making the mistake? I did extraction with Assura and its av_extracted shows the desired behaviour...
Its here
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5338964&isnumber=5338937
However its a conference paper, so many details not given.
/Noman Hai
Yes you can still use loopgain simulation methodology in cadence. However before running "stb" analysis you have to run transients till your CM is settled. An easier way is to use ideal CMFB circuit and then do can skip the transient analysis part.
My answer assumes you already have good...
you can run trasient analysis until your CMFB is settled. Now run AC analysis and in its option menu click yes "prevoppt". It should do the trick for you.
I beg to differ here.
You can use 2 8-bits ADC to get 12 bits but it won't be a 12-bit 'ADC'. Basically to get 12 bits you need sampling capacitors of about 2^4 times higher than used in a typical 8-bit implementation to satisfy thermal noise requirements. Also, opamp must have 2^4 higher gain...
Here what I used to do.
1) Type clsAdminTool at shell prompt, and you will get a > prompt
2) Type are /<you_path>/folder_name (folder name is from the directory you running the cadence). This will erase the locks.
In order to check which files have edit locks, simply type ale...
iamxo, I think you are missing very important point here. ft of an opamp can be given as ft=β gm/Cl. When you scale the stages, the load feedback factor remain constant however, the load capacitance is reduced half (assuming you scaling down by 2 approx and not taking into account unscaled...
assura rcx no technology directory found
Yes I second oermens comments as I also had the same problem and the setup suggested by oermens is the only way.
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