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Recent content by user_asic

  1. user_asic

    Lets talk about pin multiplexing

    Guys, When doing multi-FPGA designs, there are times you (or the CAD tool) inadvertently adds a non multi-cycle net or combinational net through time division multiplexing (TDM) logic after partitioning. Adding such nets to TDM logic may lead to incorrect operation. What are some of the...
  2. user_asic

    what kind of tools required for network on chip projects

    You can start here: https://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1439155 https://hal.archives-ouvertes.fr/docs/00/07/73/39/PDF/Norchip04_evain.pdf If you are a masters final year and don't know what CAD tools to use, then you shouldn't be doing a NoC-based design...just saying...
  3. user_asic

    spartan 3e running problem

    How many slices is your design using? I've seen this with my designs where after adding debugging capabilities, the design works very well. But when this feature is removed, the design completely breaks. After you remove the debug capability, you may violate some of the timing constraints or...
  4. user_asic

    Looking for ways to test FPGA logic

    I need a way to test all clbs in a virtex 4 and virtex 5 fpga. But I can't seem to find any sample designs that show how to do this. Most research papers focus on BIST techniques, which is beyond my skill level without any sample designs to look at. Can anyone point me to some sample designs...
  5. user_asic

    How to implement core from xilinx core generator?

    xilinx core generator See this: **broken link removed** page 36, Creating a CORE Generator Module
  6. user_asic

    From spartan-3 to Virtex-5

    Try to compile your design for a V5 FPGA. Thats easier :p
  7. user_asic

    How to implement core from xilinx core generator?

    xilinx core generator Have you tried using the instantiation template that is provided by core generator when you generated the module?
  8. user_asic

    cannot synthesize simple mux with design compiler

    Can you provide your synthesis report?
  9. user_asic

    RF/Microwave Jobs in Canada ?

    Ottawa is the semiconductor center in Canada.
  10. user_asic

    Looking for part time analog (and some digital) help

    I am interested in the digital side. Please provide more details or you can contact me via private message if you prefer.
  11. user_asic

    Openings in Snowbush IP, A Division of Gennum Corp.

    Are there any vacancies in the Toronto location?
  12. user_asic

    Looking to get into mixed-signal IC design (analog-digital)

    It seems there are about three good books: B. Razavi P. Gray, P. Hurst, S. Lewis, and R. Meyer R. Baker Any recommendations for someone totally new to analog cmos IC design?
  13. user_asic

    Looking to get into mixed-signal IC design (analog-digital)

    Oh okay, my apologies. I wanna design the digital and analog blocks. Can you recommend some reading materials?
  14. user_asic

    Looking to get into mixed-signal IC design (analog-digital)

    No inputs guys?
  15. user_asic

    initialise the counter with desired value verilog/vhdl

    If your synthesizer allows you to initialize a reg on power on, then you can do that. Best practice is to have a "reset" state where all regs, including your counter, are initialized to desired values.
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